发明名称 METHOD FOR TESTING MULTI-CHIP STACKED PACKAGES
摘要 Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.
申请公布号 US2013076384(A1) 申请公布日期 2013.03.28
申请号 US201113242400 申请日期 2011.09.23
申请人 CHANG KAI-JUN;POWERTECH TECHNOLOGY, INC. 发明人 CHANG KAI-JUN
分类号 G01R31/28 主分类号 G01R31/28
代理机构 代理人
主权项
地址