FAST FOURIER TRANSFORM CIRCUIT

摘要

In the present invention, a plurality of data sequences arranged along the time axis are subjected to FFT processing via a small-scale circuit. A multiplexer (11) receives a plurality of data sequences arranged along the time axis and outputs partial data of each data sequence in a predetermined data sequence order for each unit of time; a first stage butterfly computation unit (12-1) inputs the partial data that the multiplexer (11) outputs as second input data; a lag unit (13-1) provided corresponding to the first stage butterfly computation unit (12-1) inputs, in the data sequence order, the partial data that the multiplexer (11) outputs, delays the result, and outputs as the first input data of the first stage butterfly computation unit (12-1).