发明名称 |
LAYOUT FOR SEMICONDUCTOR MEMORIES |
摘要 |
A semiconductor memory includes a first conductive layer including a first pair of bit lines coupled to a first bit cell and a second conductive layer including a second pair of bit lines coupled to the first bit cell. The first and second conductive layers are vertically separated from each other.
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申请公布号 |
US2013077375(A1) |
申请公布日期 |
2013.03.28 |
申请号 |
US201113242399 |
申请日期 |
2011.09.23 |
申请人 |
LIAW JHON JHY;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
LIAW JHON JHY |
分类号 |
G11C5/06 |
主分类号 |
G11C5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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