| 摘要 |
In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
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