Integrated circuit using FD-SOI technology with shared box and a means for polarising opposite doping floorplans located in the same box

摘要

The circuit has a stack of P-type semiconductor substrates (Sub), an insulating layer (bn2) and an electronic component (n2) i.e. transistor, that is formed on a semiconductor layer. A polarization circuit is utilized for generating a bias. An insulation trench (47) is formed for separating the electronic component from a set of interconnections (vn12). A box (wl-p) having a doping type that is opposite to another doping type is arranged underneath an earth plane (gpl-n), where the box extends in the trench, and is arranged in contact with another set of interconnections. The transistor is a fully depleted silicon-on-insulator (FDSOI) transistor.