发明名称 Processing long-latency instructions in a pipelined processor
摘要 There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed before the hazard instruction is processed. The method comprises the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time. The processor includes means for performing steps a), b) and c) of the method.
申请公布号 US8407454(B2) 申请公布日期 2013.03.26
申请号 US201213487218 申请日期 2012.06.03
申请人 BERGLAS MORRIE;FOO YOONG CHERT;IMAGINATION TECHNOLOGIES, LTD. 发明人 BERGLAS MORRIE;FOO YOONG CHERT
分类号 G06F9/30;G06F7/38;G06F9/00;G06F9/40;G06F9/44 主分类号 G06F9/30
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