发明名称 |
Methods and apparatus for boolean equivalency checking in the presence of voting logic |
摘要 |
In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of the original circuit design includes a set of latches associated with the latch of the original circuit design and voting logic having inputs coupled to respective outputs of latches in the latch set; and (3) during Boolean equivalency checking (BEC), injecting an error on at most a largest minority of the inputs of the voting logic to test the voting logic function. |
申请公布号 |
US8407638(B2) |
申请公布日期 |
2013.03.26 |
申请号 |
US20090355757 |
申请日期 |
2009.01.16 |
申请人 |
ACUNA VICTOR A.;KANZELMAN ROBERT L.;MACK SCOTT H.;WILSON BRIAN C.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ACUNA VICTOR A.;KANZELMAN ROBERT L.;MACK SCOTT H.;WILSON BRIAN C. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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