发明名称 |
Method for optimizing memory controller configuration in multi-core processors using fitness metrics and channel loads |
摘要 |
The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network. |
申请公布号 |
US8407167(B1) |
申请公布日期 |
2013.03.26 |
申请号 |
US20090487957 |
申请日期 |
2009.06.19 |
申请人 |
ABTS DENNIS C.;GIBSON DANIEL;GOOGLE INC. |
发明人 |
ABTS DENNIS C.;GIBSON DANIEL |
分类号 |
G06F15/18 |
主分类号 |
G06F15/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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