发明名称 METHOD AND DEVICE FOR LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To prevent the prolongation of design period when performing a layout design while allowing a plurality of hierarchical blocks to overlap each other. <P>SOLUTION: When layout of a plurality of hierarchical blocks each including a plurality of internal elements is performed for an installation area where internal element resources, to which the internal elements can be assigned, are arranged, the following is performed: a first hierarchical block and a second hierarchical block are arranged so that, when the first hierarchical block and the second hierarchical block overlap each other in an overlapping area, the total of the number of first internal elements included in the overlapping area out of internal elements in the first hierarchical block, and the number of second internal elements included in the overlapping area out of internal elements in the second hierarchical block, is equal to or less than the number of internal element resources included in the overlapping area; and the internal element resources included in the overlapping area are assigned to the first hierarchical block and the second hierarchical block according to the ratio of the number of the first internal elements to the number of the second internal elements. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013054567(A) 申请公布日期 2013.03.21
申请号 JP20110192949 申请日期 2011.09.05
申请人 RENESAS ELECTRONICS CORP 发明人 HANDA MITSURU
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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