发明名称 |
METHOD FOR ENSURING DPT COMPLIANCE WITH AUTOROUTED METAL LAYERS |
摘要 |
A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set.
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申请公布号 |
US2013074028(A1) |
申请公布日期 |
2013.03.21 |
申请号 |
US201213622937 |
申请日期 |
2012.09.19 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
BLATCHFORD JAMES WALTER |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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