| 发明名称 |
Method For Ensuring DPT Compliance for Auto-Routed Via Layers |
| 摘要 |
A method of generating an integrated circuit with a DPT compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set.
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| 申请公布号 |
US2013072020(A1) |
申请公布日期 |
2013.03.21 |
| 申请号 |
US201213622949 |
申请日期 |
2012.09.19 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
BLATCHFORD JAMES WALTER |
| 分类号 |
G06F17/50;H01L21/768 |
主分类号 |
G06F17/50 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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