发明名称 Phase Averaging-Based Clock and Data Recovery
摘要 In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.
申请公布号 US2013070882(A1) 申请公布日期 2013.03.21
申请号 US201113239267 申请日期 2011.09.21
申请人 NEDOVIC NIKOLA;FUJITSU LIMITED 发明人 NEDOVIC NIKOLA
分类号 H03D3/24 主分类号 H03D3/24
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