| 摘要 |
<p>13. A computer accessible storage medium storing a plurality of instructions which, when executed, implement the method as recited in any of claims 10-12. 5 In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be 10 interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue. Memory * IC 10' Interconnect Fabric 1 IOP 32 CDMA 2012 Processor 22 Peripheral Flash Memory Peripheral Component 18A Interface 30 Component 18B Flash Memory Flash Memory Fig.</p> |
