| 摘要 |
Provided is a complementary metal oxide semiconductor (CMOS) inverter layout for increasing an effective channel length. The CMOS inverter layout may include first and second conductive MOS transistors respectively formed in first and second active regions, metal lines electrically connecting the first and second conductive MOS transistors, and one or more gate electrodes electrically connecting the gates of the first and second conductive MOS transistors. The widths of one or more gate electrodes may be set to a reduced and/or minimum feature size to reduce and/or minimize a process variation and a layout area of the CMOS inverter. Also, the first and second conductive MOS transistors may be connected in series via the metal lines to increase an effective channel length, thereby realizing a layout of the CMOS inverter having a longer delay than a conventional CMOS inverter. |
