| 摘要 |
Flip-flops 201 to 206 constitute a scan path shift register. During shift mode operation, a clock signal CLK is supplied to clock terminals of the flip-flops 201, 203, and 205, a signal obtained by having an inverted clock control circuit 303 reverse the phase of the clock signal CLK is supplied to clock terminals of the flip-flops 202 and 206, and a normal/inverted clock control circuit 404 supplies a signal having the same phase as the clock signal CLK to a clock terminal of the flip-flop 204 having no sufficient setup time. |
