发明名称 Multi-bit error correction method and apparatus based on a BCH code and memory system
摘要 Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
申请公布号 US8402352(B2) 申请公布日期 2013.03.19
申请号 US20100704231 申请日期 2010.02.11
申请人 LI YUFEI;LU YONG;WANG YING;YANG HAO;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LI YUFEI;LU YONG;WANG YING;YANG HAO
分类号 H03M13/00 主分类号 H03M13/00
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