发明名称 Semiconductor memory device with memory cells having charge accumulation layer
摘要 According to one embodiment, a semiconductor memory device includes memory cells, a memory cell array, a word line, a bit line, a source line, a row decoder, a sense amplifier, and a first MOS transistor. The word line is connected to gates of the memory cells. The bit line is electrically connected to drains of the memory cells. The source line is electrically connected to sources of the memory cells. The row decoder selects the word line. The sense amplifier senses and amplifies data read onto the bit line in a read operation. The first MOS transistor is capable of connecting a well region where the memory cells are formed with the source line and is arranged between the row decoder or the sense amplifier and the memory cell array.
申请公布号 US8400837(B2) 申请公布日期 2013.03.19
申请号 US20100797965 申请日期 2010.06.10
申请人 EDAHIRO TOSHIAKI;KABUSHIKI KAISHA TOSHIBA 发明人 EDAHIRO TOSHIAKI
分类号 G11C16/06 主分类号 G11C16/06
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