发明名称 |
Technique for automatically assigning placement for pipeline registers within code generated from a program specification |
摘要 |
A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration. |
申请公布号 |
US8402449(B1) |
申请公布日期 |
2013.03.19 |
申请号 |
US20080972117 |
申请日期 |
2008.01.10 |
申请人 |
BISWAS PARTHA;RAGHAVAN VIJAYA;ZHAO ZHIHONG;THE MATHWORKS, INC. |
发明人 |
BISWAS PARTHA;RAGHAVAN VIJAYA;ZHAO ZHIHONG |
分类号 |
G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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