| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the influence of spurious components in a high frequency signal processing device comprising a digital PLL circuit and a radio communication system. <P>SOLUTION: In a digital PLL circuit comprising, for example, a digital phase comparison unit DPFD, a digital low-pass filter DLPF, a digital control oscillation unit DCO, a multi-module driver unit (frequency divider unit) MMD, the clock frequency of a clock signal CK<SB POS="POST">DLPF</SB>of the DLPF is configured to be selectable from multiple alternatives. The clock frequency is selected from frequencies of integral multiple of a reference oscillation signal Fref depending on which frequency band on a standard is set to an oscillation output signal RFdco of the DCO. <P>COPYRIGHT: (C)2013,JPO&INPIT |
