| 摘要 |
In the present invention, when performing write-leveling, in order to avoid lengthening initialization time, a write-leveling control unit (250) adjusts the delay amounts of a DQS control unit (242) and a DQ control unit (244) , at first, within a range of less than one clock cycle. Then, with respect to each SDRAM (282), a read-data row acquired by performing a read after a write of an expected value data row is compared with the expected value data row, and depending upon the comparison result, the delay amounts of the DQS control unit (242) and the DQ control unit (244) are adjusted in clock-cycle units. At the above write-time, control is performed so that the DQS control unit (242) outputs a data strobe signal (DQS) which is 2 x M clock cycles (M: an integer greater than or equal to 1) longer than a burst length defined according to a specification, and the DQ control unit (244) adds M units each of data before and after a number of units of expected value data rows that match the above burst length in order to output the data. |
