| 摘要 |
A data processor (1) includes a plurality of oscillation circuits (13 and 24) that individually generate a first clock signal (HCK) and a second clock signal (LCK) with a lower frequency, in which a CPU (10) performs data processing in synchronization with the oscillation output of an oscillation circuit selected by a clock switching circuit (22). In a state where the low power consumption mode is set, the data processor stops the first clock signal and maintains the oscillation of the second clock signal, selects whether or not to initiate the oscillation of the first clock signal in response to the trigger to cancel the low power consumption mode, and initiates the oscillation of the first clock signal without the CPU interrupt process which is enabled by the cancellation of the low power consumption mode. During the time period of the power-on reset for returning from a power-off state, oscillation of the first clock signal is initiated on the condition that the externally provided power-on trigger is a predetermined trigger, and the oscillation of the first clock signal is inhibited in case that the trigger is a trigger other than the predetermined trigger.
|
