| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve high-speed access while reducing trimming time and a fuse-element-occupied area. <P>SOLUTION: A semiconductor device comprises: a row fuse circuit 21 that stores the address of a defective word line; a column fuse circuit 22 that stores the address of a defective bit line; a row decoder 11 that selects a word line WL or a redundant word line RWL on the basis of a row address XADD or an address RXADD read from the row fuse circuit 21; and a column decoder 12 that selects a bit line BL or a redundant bit line RBL on the basis of a column address YADD or an address RXADD read from the column fuse circuit 22. The row decoder 11, the row fuse circuit 21, and the column fuse circuit 22 are arranged along the long side 10a of a memory cell array 10, and the column decoder 12 is arranged along the short side 10b of the memory cell array 10. <P>COPYRIGHT: (C)2013,JPO&INPIT |
