发明名称 |
ELECTRICAL TEST STRUCTURE APPLYING 3D-ICS BONDING TECHNOLOGY FOR STACKING ERROR MEASUREMENT |
摘要 |
A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern. |
申请公布号 |
US2013062776(A1) |
申请公布日期 |
2013.03.14 |
申请号 |
US201113294183 |
申请日期 |
2011.11.11 |
申请人 |
CHEN KUAN-NENG;LI SHIH-WEI;NATIONAL CHIAO TUNG UNIVERSITY |
发明人 |
CHEN KUAN-NENG;LI SHIH-WEI |
分类号 |
H01L23/48 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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