发明名称
摘要 The method involves comparing an output voltage of an analog-digital converter (20) with a voltage stored on a low-pass loop filter (15) to automatically calibrate a gain of the converter. A low frequency phase lock loop is closed in a modulation phase. An output of the converter is connected to an input of a voltage controlled oscillator (10) for modulating high frequency data at two points using a series of command words provided at the converter and a modulator (11) of the phase locked loop, where the words are derived from a Gaussian type digital filter (30) forming a data signal (31). An independent claim is also included for a frequency synthesizer for implementing a self-calibrating method, comprising a low frequency phase locked loop.
申请公布号 JP5161184(B2) 申请公布日期 2013.03.13
申请号 JP20090231370 申请日期 2009.10.05
申请人 发明人
分类号 H03L7/08;H03C3/00;H03L7/18 主分类号 H03L7/08
代理机构 代理人
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