| 摘要 |
A configuration for biasing conductive array lines in a two-terminal cross-point memory array is disclosed. The configuration includes applying a read voltage to a selected X-conductive array line while applying an un-select voltage thru a biasing element to a remaining plurality of un-selected X-conductive array lines. A plurality of Y-conductive array lines are initially biased to some voltage (e.g., 0V) and then allowed to float unbiased after a predetermined amount of time has passed, some event has occurred, or both. As one example the event that triggers the floating of the plurality of Y-conductive array lines can be the read voltage reaching a predetermined magnitude. The array can be formed BEOL and include a plurality of two-terminal memory cells with each memory cell including a memory element and optionally a non-ohmic device (NOD) that are electrically in series with each other and with the two terminals of the memory cell. |
