发明名称 Distributing clock associated with a wired data connection over wireless interfaces using frequency correction at the transmitter side
摘要 A clock extractor extracts clock frequency f2, from a wired data connection feeding the transmitter with data clocked at the clock frequency f2. A clock error estimator estimates clock frequency error between the clock frequency f2 and a clock frequency f1 derived from a local clock of the transmitter. Clock adder adds the clock frequency error to the clock frequency f1, resulting in a synthesized clock frequency f2. A modulator uses the synthesized clock frequency f2, to modulate a data stream into a modulated signal.
申请公布号 US8396178(B1) 申请公布日期 2013.03.12
申请号 US20100873125 申请日期 2010.08.31
申请人 MAYSEL BORIS;LEIBA YIGAL;SIKLU COMMUNICATION LTD. 发明人 MAYSEL BORIS;LEIBA YIGAL
分类号 H04L7/00 主分类号 H04L7/00
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