| 摘要 |
<p>Disclosed in an automatic tester (40), comprising a first signal converter (41) for converting, using a conversion clock signal (CLK), a signal from a digital signal domain to an analog signal domain to obtain an analog stimulus signal (STIM); a first signal path (42) for forwarding the analog stimulus signal (STIM) from the first signal converter (41) to a second signal converter (43), which is adapted to convert the analog stimulus signal (STIM) back from the analog signal domain to the digital signal domain; and a second signal path (44) for forwarding the conversion clock signal (CLK) or a signal derived thereof from the first signal converter (41) to the second signal converter (43), such that a difference (?t) between a propagation delay of an analog stimulus signal (STIM) in response to a clock cycle of the conversion clock signal (CLK) via the first signal path (42) and a propagation delay of the conversion clock signal of said clock cycle via the second signal path (44) is within a predetermined tolerance range, such that a relative jitter between the analog stimulus signal (STIM) and the forwarded conversion clock signal (CLK) or the signal derived thereof is kept minimal.</p> |
