MERGING UNIT EMULATOR FOR DETECTION IN SMART SUBSTATION

摘要

A merging unit emulator for detection in a smart substation includes a main circuit board, a main circuit board interface plug, an interface driving chip, a central processing unit (CPU) module, a field programmable gate array (FPGA),a memory clock module and a fiber optical transceiver. The memory clock module includes a nonvolatile random access memory (NVRAM), a flash memory (FLASH) and a real time chip (RTC). The sampling values are calculated by the core module FPGA of the merging unit emulator based upon input signals. The merging unit has the features of stable operation, less power loss, precise time labeling and less time delay for a sampling value message.