发明名称 DETERMINING AN EFFECTIVE STRESS LEVEL ON A PROCESSOR
摘要 In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.
申请公布号 WO2013032705(A2) 申请公布日期 2013.03.07
申请号 WO2012US50895 申请日期 2012.08.15
申请人 INTEL CORPORATION;SHAPIRA, DORIT;ROTEM, EFRAIM;MORAN, DOUGLAS, R. 发明人 SHAPIRA, DORIT;ROTEM, EFRAIM;MORAN, DOUGLAS, R.
分类号 G06F1/00;G06F1/26;G06F13/00 主分类号 G06F1/00
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