| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a fast level-shifting circuit with a low duty cycle distortion and a high supply voltage margin. <P>SOLUTION: A level shifter 100 includes an inverting circuit 104, a cross-coupled level shifting latch 102, and an SR logic gate latch 103. The first and second outputs of the level shifting latch 102 are coupled to a set (S) input node 121 and a reset (R) input node 120 of the SR logic gate latch 103. The inverting circuit 104 respectively supplies a noninverted signal and an inverted signal to a first input node 112 and a second input node 113 of the level shifting latch 102. A low-to-high transition of an input signal resets the SR logic gate latch 103, whereas a high-to-low transition sets the SR logic gate latch 103. <P>COPYRIGHT: (C)2013,JPO&INPIT |
