| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten a simulation time. <P>SOLUTION: A verification support device detects CDC (Clock Domain Crossing) jitter J1 under the execution of (1) in a simulation 101 giving a predetermined input pattern to circuit information of a verification object circuit. The verification support device duplicates the execution state of the simulation 101 in the case of detecting the CDC jitter J1. The verification support device sets the output of an element in a second clock domain in the executing state of the duplicated simulation 101 to a logical value which is different from the detected output value. The verification support device exclusively executes a simulation 102 (second simulation) based on the set execution state with the simulation 101. A logical simulator is not able to execute those several simulations in parallel. Therefore, while one simulation is being executed by the logical simulator, the other simulation is put in a stand-by state for execution. <P>COPYRIGHT: (C)2013,JPO&INPIT |
