| 摘要 |
PURPOSE: A method for manufacturing a semiconductor device with a damascene bit line is provided to form an air gap between a bit line and a storage node contact plug to reduce parasitic capacitance due to the low dielectric constant of the air gap. CONSTITUTION: A first landing plug(24A) and a second landing plug(24B) are formed in an active region(23). A storage node contact plug(28A,28B) is formed on the first landing plug. A bit line(35A) is formed on the second landing plug. An air gap(34) and a spacer(32) are formed between the storage node contact plug and the bit line. A bit line hard mask layer(36) is formed on the bit line. A capping layer(35B) seals the upper side of the air gap. A hard mask film pattern(29) is formed on the upper sides of an interlayer dielectric layer(25) and the storage node contact plug.
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