| 摘要 |
<P>PROBLEM TO BE SOLVED: To attain either division arithmetic processing of a characteristic P or a characteristic 2, without having to increase the circuit scale by eliminating the limit of divisors. <P>SOLUTION: Five bits of higher orders of a dividend (A) are seen by being shifted sequentially, from higher-order digits of the dividend (A) stored in a shift register 12. A register 30 is a present maximum order value; and when it is "1", subtraction is executed. When the value of the register 30 is "1", AND elements 32-38 output the value of a divisor (B) from registers 14-22; and subtraction is executed in EXCLUSIVE OR elements 40-46. The output of the register 30 is stored in a shift register 48, as it is and is a quotient. Such a processing operation is executed, until all the bits of the dividend (A) are output; and if the dividend (A) is m bits, operation is halted at m clock. Then, the values of registers 24-30 become a remainder, and the value of the register 30 becomes the most-significant digit (MSB). <P>COPYRIGHT: (C)2010,JPO&INPIT |
