发明名称 Methods for making multi-chip packaging using an interposer
摘要 In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.
申请公布号 US8387240(B2) 申请公布日期 2013.03.05
申请号 US20100955816 申请日期 2010.11.29
申请人 MUTHUKUMAR SRIRAM;MANCERA RAUL;TOMITA YOSHIHIRO;HWANG CHI-WON;INTEL CORPORATION 发明人 MUTHUKUMAR SRIRAM;MANCERA RAUL;TOMITA YOSHIHIRO;HWANG CHI-WON
分类号 H01K3/10 主分类号 H01K3/10
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