发明名称 Dense nanoscale logic circuitry
摘要 One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.
申请公布号 US8390323(B2) 申请公布日期 2013.03.05
申请号 US200913256234 申请日期 2009.04.30
申请人 STRUKOV DMITRI BORISOVICH;KUEKES PHILIP J.;HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 STRUKOV DMITRI BORISOVICH;KUEKES PHILIP J.
分类号 H03K19/177 主分类号 H03K19/177
代理机构 代理人
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