PURPOSE: A memory device and apparatuses including the same are provided to stabilize a memory cell property by controlling the activation timing of a control signal. CONSTITUTION: An access control circuit(115) accesses a memory cell array for performing a read operation or a write operation. A control signal generating circuit(131) generates a control signal for controlling the operation of an access control circuit. A variable delay circuit(133) generates a delay signal by delaying a clock signal according to an external signal. The control signal generating circuit controls the activation timing of the control signal in response to a delay signal. [Reference numerals] (110) Memory cell array; (131) Control signal generating circuit; (160) Data input/output circuit
