发明名称 |
Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns |
摘要 |
A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line. |
申请公布号 |
US8389357(B2) |
申请公布日期 |
2013.03.05 |
申请号 |
US201113052728 |
申请日期 |
2011.03.21 |
申请人 |
KAKOSCHKE RONALD;NIRSCHL THOMAS;SHUM DANNY;SCHRUEFER KLAUS;INFINEON TECHNOLOGIES AG |
发明人 |
KAKOSCHKE RONALD;NIRSCHL THOMAS;SHUM DANNY;SCHRUEFER KLAUS |
分类号 |
H01L21/336;G11C16/04;H01L27/115;H01L29/861 |
主分类号 |
H01L21/336 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|