| 摘要 |
<P>PROBLEM TO BE SOLVED: To suggest a design method for reducing clock skew among a plurality of macros loaded on an LSI. <P>SOLUTION: In a semiconductor integrated circuit design method, based on circuit information on an integrated circuit including a plurality of lower layer circuits, output of logic circuits for supplying clocks to flip-flops included in the lower layer circuits is extracted as clock points, circuit configurations of the logic circuits using the extracted clock points as output are recognized, among the extracted clock points, a clock point is selected from a first lower layer circuit, a clock point is selected from a second lower layer circuit, and circuit configurations of the logic circuits using the respective clock points as output are compared with each other. When comparison results match to each other, one of the logic circuits for outputting the two selected clock points is deleted, and the two clock points are integrated by replacing the one deleted clock point by output of the other logic circuit. <P>COPYRIGHT: (C)2013,JPO&INPIT |
