发明名称 OUTPUT CONTROL SCAN FLIP-FLOP, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME, AND DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 An output control scan flip-flop according to the present invention includes a first scan flip-flop that captures first data in a first mode and second data in a second mode in synchronization with a clock signal to output the data that is captured, a second scan flip-flop that captures the data output from the first scan flip-flop in the second mode in synchronization with a clock signal to output the data that is captured, and a gating circuit that generates the data output from the first scan flip-flop in the first mode as output data, and generates output data having a change rate of a logic value lower than a change rate of a logic value of the data output from the first scan flip-flop based on the data output from each of the first scan flip-flop and the second scan flip-flop in the second mode.
申请公布号 US2013055040(A1) 申请公布日期 2013.02.28
申请号 US201213568943 申请日期 2012.08.07
申请人 KIMURA HAYATO;RENESAS ELECTRONICS CORPORATION 发明人 KIMURA HAYATO
分类号 G01R31/3177;G06F11/25 主分类号 G01R31/3177
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