发明名称 |
DIGITAL SIGNAL CODING APPARATUS, DIGITAL SIGNAL DECODING APPARATUS, DIGITAL SIGNAL ARITHMETIC CODING METHOD AND DIGITAL SIGNAL ARITHMETIC DECODING METHOD |
摘要 |
<p>DIGITAL SIGNAL CODING APPARATUS, DIGITAL SIGNAL DECODING APPARATUS, DIGITAL SIGNAL ARITHMETIC CODING METHOD AND DIGITAL SIGNAL ARITHMETIC DECODING METHODIn a bit stream syntax containing compressed video slice data for compressed video data of a5 slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether aregister value, which designates a status of a codeword occurring in an arithmetic coding process,10 should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the nexttransmission unit, only when the register reset15 flag indicates that the register should not be reset.Fig. 3</p> |
申请公布号 |
SG187281(A1) |
申请公布日期 |
2013.02.28 |
申请号 |
SG20110053873 |
申请日期 |
2003.04.10 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SHUNICHI SEKIGUCHI;YOSHIHISA YAMADA;KOHTARO ASAI |
分类号 |
G06T9/00;H03M7/40;H04N7/24;H04N7/52;H04N19/00;H04N19/105;H04N19/13;H04N19/174;H04N19/46;H04N19/51;H04N19/625;H04N19/70;H04N19/91 |
主分类号 |
G06T9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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