发明名称 CIRCUIT OPERATION ANALYSIS METHOD, CIRCUIT OPERATION ANALYSIS DEVICE AND CIRCUIT OPERATION ANALYSIS PROGRAM
摘要 <p>Provided is a circuit operation analysis method that can generate a test pattern with a higher operation ratio and derive a larger peak power consumption, while preventing processing time from becoming very large, and preventing required memory volume from increasing. This circuit operation analysis method comprises: a maximum change extraction process that receives input of circuit wiring information to be analyzed and input of a circuit test pattern to be applied to said circuit wiring information, varies a measurement interval in the circuit test pattern, and from the circuit test pattern, extracts an interval for which the operation speed of a flip-flop contained in the circuit wiring information is a maximum; a pattern generation process that generates a second circuit test pattern on the basis of a pattern contained in the aforementioned interval; and a power consumption analysis process that analyzes the power consumption for the circuit wiring information when the second circuit test pattern is applied.</p>
申请公布号 WO2013027738(A1) 申请公布日期 2013.02.28
申请号 WO2012JP71108 申请日期 2012.08.15
申请人 NEC CORPORATION;NAKAMURA, YUICHI 发明人 NAKAMURA, YUICHI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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