发明名称 |
3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING |
摘要 |
There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
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申请公布号 |
US2013049824(A1) |
申请公布日期 |
2013.02.28 |
申请号 |
US201113217349 |
申请日期 |
2011.08.25 |
申请人 |
KIM JAE-JOON;LIN YU-SHIANG;PANG LIANG-TECK;SILBERMAN JOEL A.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KIM JAE-JOON;LIN YU-SHIANG;PANG LIANG-TECK;SILBERMAN JOEL A. |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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