| 摘要 |
A semiconductor memory device includes a memory core configured to sequentially activate first and second banks in response to first and second bank active signals which are sequentially enabled in response to first and second enable signals when a self-refresh operation is to be performed, select a word line by row addresses, and perform a refresh operation for memory cells which are connected with the word line; and an address counter configured to perform a counting operation for the row addresses in response to a counter signal, and interrupt the counting operation for the row addresses in a case where both the first and second banks are not activated when the self-refresh operation is ended. |
