发明名称 HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL
摘要 A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.
申请公布号 US2013049799(A1) 申请公布日期 2013.02.28
申请号 US201213663753 申请日期 2012.10.30
申请人 LSI CORPORATION;LSI CORPORATION 发明人 BHAKTA DHARMESH;LIM HONG-HIM;KONG CHENG-GANG;RANDAZZO TODD
分类号 H03K19/003 主分类号 H03K19/003
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