发明名称 |
Methods for Forming Interconnect Structures of Integrated Circuits |
摘要 |
A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask.
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申请公布号 |
US2013052818(A1) |
申请公布日期 |
2013.02.28 |
申请号 |
US201113220245 |
申请日期 |
2011.08.29 |
申请人 |
SHIH PO-CHENG;KO CHUNG-CHI;LIN KENG-CHU;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
SHIH PO-CHENG;KO CHUNG-CHI;LIN KENG-CHU |
分类号 |
H01L21/768 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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