| 摘要 |
A differential capacitive transducer system is disclosed that includes first and second capacitive cores and a chopping system. The first core a first input coupled to a first capacitor, a second input coupled to a second capacitor, and a first output. The second core includes a third input coupled to a third capacitor, a fourth input coupled to a fourth capacitor, and a second output. The chopping system has first and fourth inputs coupled to positive signals, and second and third inputs coupled to negative signals. As the chopping system switches between high and low states, it couples the core inputs to different polarity signals reducing charge buildup. The different polarity signals can have substantially same magnitudes. Chopper clock and main clock frequencies can be selected to provide substantially zero average voltages at the core inputs. The system can include an integrator circuit and differential summing circuits.
|
