发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS
摘要 When a bus stop request control unit issues a module-specific bus stop request signal, a bus stop control unit coupled to a bus slave determines a module that serves as a bus master of the bus slave and on which the bus slave is dependent, for example, on the basis of information in a dependence setting register. The bus stop control unit then outputs a prior bus stop request signal to the module on which the bus slave is dependent, so as to stop use of a bus of the module. Upon receipt of a module-specific bus stop completion signal indicating that processing of stop of the bus of the module on which the bus slave is dependent is complete, the bus stop control unit outputs a module-specific bus stop request signal to the module which serves as a bus slave and whose bus is to be stopped.
申请公布号 US2013054855(A1) 申请公布日期 2013.02.28
申请号 US201213585140 申请日期 2012.08.14
申请人 YAMASHITA HAJIME;RENESAS ELECTRONICS CORPORATION 发明人 YAMASHITA HAJIME
分类号 G06F13/40 主分类号 G06F13/40
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