| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer that reduces cumulative jitter by improving the accuracy of decimal multiplication. <P>SOLUTION: The frequency synthesizer includes a phase comparator 1, a charge pump 2, a low pass filter 3, a voltage-controlled oscillator 4, and a feedback circuit for decimally dividing the frequency of an output clock signal of the voltage-controlled oscillator to generate a feedback clock signal. The feedback circuit includes a variable frequency divider 5 for dividing the frequency of the output clock signal of the voltage-controlled oscillator 4, a multiplexer 7 for selecting a clock signal of one phase from clock signals of eight phases of the voltage-controlled oscillator 4, and a retiming circuit (DFF circuits 8, 9 and AND circuit 10) for retiming a clock signal from the variable frequency divider 5 in accordance with the clock signal of the specific phase selected by the multiplexer 7. <P>COPYRIGHT: (C)2013,JPO&INPIT |
