| 摘要 |
The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals.
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