| 摘要 |
A computer-readable medium stores a verification support program that causes a computer to execute a process that includes executing a first simulation of applying a given input pattern to circuit information of a circuit under test having a first clock domain and a second clock domain that receives asynchronously a signal from the first clock domain; detecting during execution of the first simulation, an output value that is a random value output by an element in the second clock domain; copying the execution state of the first simulation at the time of detection of the output value; setting in the copied execution state of the first simulation, output of the element in the second clock domain, to a logic value that is different from the detected output value; and executing, exclusive of the first simulation, a second simulation that is based on the set execution state. |
